d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1991 integrated circuits 74hc/hct594 8-bit shift register with output register for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1991 2 philips semiconductors product speci?cation 8-bit shift register with output register 74hc/hct594 features synchronous serial input and output 8-bit parallel output shift and storage register have independent direct clear and clocks 100 mhz (typ.) output capability: C parallel outputs: bus driver C serial outputs: standard i cc category: msi applications serial-to parallel data conversion remote control holding register description the 74hc/hct594 are high-speed, si-gate cmos devices, and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct594 contain an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit d-type storage register. separate clocks and direct overriding clears are provided on both the shift and storage registers. a serial output (q 7 ) is provided for cascading purposes. both the shift and storage register clocks are positive-edge triggered. if the user wishes to connect both clocks together, the shift register will always be one count pulse ahead of the storage register. quick reference data gnd = 0 v: t amb = 250 c; t r = t f = 6 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d = c pd v cc 2 f i + ? (c l v cc 2 f o ), where: f i = input frequency in mhz; f o = output frequency in mhz; ? (c l v cc 2 f o ) = sum of the outputs; c l = output load capacitance in pf; v cc = supply voltage in v. 2. for hc, the condition is v i = gnd to v cc ; for hct, the condition is v i = gnd to v cc - 1.5 v. ordering information symbol parameter conditions typical unit hc hct t phl /t plh propagation delay c l = 15 pf; v cc = 5 v sh cp to q 7 1315ns st cp to q n 13 15 ns sh r to q n 11 14 ns st r to q n 11 14 ns f max maximum clock frequency sh cp ,st cp 100 100 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 84 89 pf extended type number packages pins pin position material code pc74hc/hct594p 16 dil plastic sot38c, p pc74hc/hct594t 16 so plastic sot109a
december 1991 3 philips semiconductors product speci?cation 8-bit shift register with output register 74hc/hct594 pinning symbol pin description q 0 to q 7 15 & 1 to 7 parallel data outputs gnd 8 ground (0 v) q 7 9 serial data output sh r 10 shift register reset (active low) sh cp 11 shift register clock input st cp 12 storage register clock input st r 13 storage register reset active (low) d s 14 serial data input v cc 16 supply voltage fig.1 logic symbol. g e mbc319 sh cp st cp q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 sh r st r d s 14 10 13 11 12 15 9 1 2 3 4 5 6 7 q 7 ' fig.2 pin configuration. g e 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 594 q 1 q 2 q 3 q 4 q 5 q 6 q 7 q 7 ' q 0 gnd sh r sh cp st cp st r d s v cc mbc318 fig.3 iec logic symbol. halfpage mbc322 - 1 sh cp st cp q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 sh r st r d s 15 9 1 2 3 4 5 6 7 1d 2d c1/ 10 11 14 c2 12 13 2 r srg8 r 1 q 7 '
december 1991 4 philips semiconductors product speci?cation 8-bit shift register with output register 74hc/hct594 function table note 1. h = high voltage level l = low voltage level - = low-to-high transition nc = no change x = dont care. inputs outputs function sh cp st cp sh r st r d s q 7 q n x x l x x l nc a low level on sh r only affects the shift registers. xxxl xncla low level on st r only affects the storage registers. x - l h x l l empty shift register loaded into storage register. - xhxhq 6 nc logic high level shifted into shift register stage 0. contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal q 6 ) appears on the serial output (q 7 ). x - hhxncq n contents of shift register stages (internal q n ) are transferred to the storage register and parallel output stages. -- hhxq 6 nq n contents of shift register shifted through. previous contents of shift register transferred to the storage register and the parallel output stages. fig.4 functional diagram. handbook, halfpage mbc320 sh cp st cp q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 sh r st r d s 14 10 13 11 12 15 9 1234567 8-stage shift register 8-bit storage register q 7 '
december 1991 5 philips semiconductors product speci?cation 8-bit shift register with output register 74hc/hct594 fig.5 logic diagram. handbook, full pagewidth mbc321 - 1 sh cp st cp q 0 q 1 q 2 q 3 q 4 q 5 q 6 sh r st r d s d q cp ffsh 0 r stage 0 d q cp ffst 0 r stages 1 to 6 dq q 7 dq cp ffsh 7 r stage 7 d q cp ffst 7 r q 7 ' fig.6 timing diagram. handbook, full pagewidth mbc323 - 1 sh cp st cp q ' 7 q 0 q 1 q 6 q 7 sh r st r d s
december 1991 6 philips semiconductors product speci?cation 8-bit shift register with output register 74hc/hct594 dc characteristics for 74hc for the dc characteristics, see 74hc/hct/hcu/hcmos logic family specifications . output capability: parallel outputs, bus driver; serial output, standard. i cc category: msi. ac characteristics for 74hc gnd = 0 v; t r = t f = 6 ns; c l = 50 pf. symbol parameter t amb ( c) unit test conditions +25 - 40 to +85 - 40 to +125 v cc (v) waveforms min. typ. max. min. max. min. max. t phl /t plh propagation delay sh cp to q 7 - - - 44 16 14 150 30 26 - - - 185 37 31 - - - 225 45 38 ns ns ns 2.0 4.5 6.0 fig.7 propagation delay st cp to q n - - - 44 16 14 150 30 26 - - - 185 37 31 - - - 225 45 38 ns ns ns 2.0 4.5 6.0 fig.8 t phl propagation delay sh r to q 7 - - - 39 14 12 150 30 26 - - - 185 37 31 - - - 225 45 38 ns ns ns 2.0 4.5 6.0 fig.11 propagation delay st r to q n - - - 39 14 12 125 25 21 - - - 155 31 26 - - - 185 37 31 ns ns ns 2.0 4.5 6.0 fig.12 t w shift clock pulse width high or low 80 16 14 10 4 3 - - - 100 20 17 - - - 120 24 20 - - - ns ns ns 2.0 4.5 6.0 fig.7 storage clock pulse width high or low 80 16 14 10 4 3 - - - 100 20 17 - - - 120 24 20 - - - ns ns ns 2.0 4.5 6.0 fig.8 shift and storage reset pulse width high or low 80 16 14 14 5 4 - - - 100 20 17 - - - 120 24 20 - - - ns ns ns 2.0 4.5 6.0 fig.11 and fig.12 t su set-up time d s to sh cp 100 20 17 10 4 3 - - - 125 25 21 - - - 150 30 26 - - - ns ns ns 2.0 4.5 6.0 fig.9 set-up time sh r to st cp 100 20 17 14 5 4 - - - 125 25 21 - - - 150 30 26 - - - ns ns ns 2.0 4.5 6.0 fig.10 set-up time sh cp to st cp 100 20 17 17 6 5 - - - 125 25 21 - - - 150 30 26 - - - ns ns ns 2.0 4.5 6.0 fig.8
december 1991 7 philips semiconductors product speci?cation 8-bit shift register with output register 74hc/hct594 t h hold time d s to sh cp 25 5 4 - 8 - 3 - 2 - - - 30 6 5 - - - 35 7 6 - - - ns ns ns 2.0 4.5 6.0 fig.9 t rem removal time sh r to sh cp , st r to st cp 50 10 9 - 14 - 5 - 4 - - - 65 13 11 - - - 75 15 13 - - - ns ns ns 2.0 4.5 6.0 fig.11 and fig.12 f max maximum clock frequency sh cp or st cp 6.0 30 35 30 92 109 - - - 4.8 24 28 - - - 4.0 20 24 - - - mhz mhz mhz 2.0 4.5 6.0 fig.7 and fig.8 symbol parameter t amb ( c) unit test conditions +25 - 40 to +85 - 40 to +125 v cc (v) waveforms min. typ. max. min. max. min. max.
december 1991 8 philips semiconductors product speci?cation 8-bit shift register with output register 74hc/hct594 dc characteristics for 74hct for the dc characteristics, see 74hc/hct/hcu/hcmos logic family specifications . output capability: parallel outputs, bus driver; serial output, standard. i cc category: msi. note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the following table. input unit load coefficient d s 0.25 sh r 1.50 sh cp 1.50 st cp 1.50 st r 1.50 ac characteristics for 74hct gnd = 0 v; t r = t f = 6 ns; c l = 50 pf. symbol parameter t amb ( c) unit test conditions +25 - 40 to +85 - 40 to +125 v cc (v) waveforms min. typ. max. min. max. min. max. t phl /t plh propagation delay sh cp to q 7 - 18 32 - 40 - 48 ns 4.5 fig.7 propagation delay st cp to q n - 18 32 - 40 - 48 ns 4.5 fig.8 t phl propagation delay sh r to q 7 - 17 30 - 38 - 45 ns 4.5 fig.11 propagation delay st r to q n - 17 30 - 38 - 45 ns 4.5 fig.12 t w shift clock pulse width high or low 16 4 - 20 - 24 - ns 4.5 fig.7 storage clock pulse width high or low 16 4 - 20 - 24 - ns 4.5 fig.8 shift and storage reset pulse width high or low 16 6 - 20 - 24 - ns 4.5 fig.11 and fig.12 t su set-up time d s to sh cp 20 4 - 25 - 30 - ns 4.5 fig.9 set-up time sh r to st cp 20 6 - 25 - 30 - ns 4.5 fig.10 set-up time sh cp to st cp 20 7 - 25 - 30 - ns 4.5 fig.8 t h hold time d s to sh cp 5 - 3 - 6 - 7 - ns 4.5 fig.9 t rem removal time sh r to sh cp , st r to st cp 10 - 5 - 13 - 15 - ns 4.5 fig.11 and fig.12 f max maximum clock frequency sh cp or st cp 30 92 - 24 - 20 - mhz 4.5 fig.7 and fig.8
december 1991 9 philips semiconductors product speci?cation 8-bit shift register with output register 74hc/hct594 ac waveforms fig.7 waveforms showing the shift clock (sh cp ) to output (q 7 ) propagation delays, the shift clock pulse width and the maximum shift clock frequency. (1) hc: v m = 50%; v i = gnd to v cc hct: v m = 1.3 v; v i = gnd to 3 v fig.8 waveforms showing the storage clock (st cp ) to output (q n ) propagation delays, the storage clock pulse width, maximum storage clock frequency and the shift clock to storage clock set-up time. (1) hc: v m = 50%; v i = gnd to v cc hct: v m = 1.3 v; v i = gnd to 3 v v m (1) t w 1/ f max v m (1) v m (1) t su t plh q outputs n st input cp sh input cp t phl mla512 fig.9 waveforms showing the data set-up and hold times for the d s input. (1) hc: v m = 50%; v i = gnd to v cc hct: v m = 1.3 v; v i = gnd to 3 v fig.10 waveforms showing the set-up time from shift reset ( sh r ) to storage clock (st cp ). (1) hc: v m = 50%; v i = gnd to v cc hct: v m = 1.3 v; v i = gnd to 3 v handbook, halfpage mbc326 v m (1) v m (1) t v m (1) st input cp q outputs sh input r su n
december 1991 10 philips semiconductors product speci?cation 8-bit shift register with output register 74hc/hct594 fig.11 waveforms showing the shift reset ( sh r ) pulse width, the shift reset to output (q 7 ) propagation delay and the shift reset to shift clock (sh cp ) removal time. (1) hc: v m = 50%; v i = gnd to v cc hct: v m = 1.3 v; v i = gnd to 3 v handbook, halfpage mbc324 v m (1) t phl v m (1) t rem t w v m (1) sh input cp q ' output 7 sh input r fig.12 waveforms showing the storage reset ( st r ) pulse width, the storage reset to outputs (q n ) propagation delay and the storage reset to storage clock (st cp ) removal time. (1) hc: v m = 50%; v i = gnd to v cc hct: v m = 1.3 v; v i = gnd to 3 v handbook, halfpage mbc325 - 1 v m (1) t phl v m (1) t rem t w v m (1) st input cp q outputs n st input r package outlines see 74hc/hct/hcu/hcmos logic package outlines .
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